High density complementary metal oxide silicon (CMOS) circuits require advanced isolation techniques. Local Oxidation of Silicon (LOCOS) has been used for several years for isolation. In this technique silicon dioxide is grown on the silicon field regions between devices, with silicon nitride preventing oxide growth on the silicon regions that will become device channels and junctions. LOCOS is not suitable for isolating very small submicron transistors, because the oxide growth will encroach laterally beneath the nitride masking layer for a distance that will substantially reduce small device dimensions.
More recently shallow trench isolation (STI) has become popular for submicron isolation. In this technique a shallow trench is etched in the silicon surrounding the active device, the trench is overfilled with silicon dioxide, and chemical mechanical polishing is used to planarize the surface to the original silicon surface. STI is not without problems: 1- The silicon etch can damage the silicon. 2- Source to drain leakage can develop along the sharp corner at the edge of the silicon. 3- The gate oxide breakdown voltage can be lowered along this sharp corner.